C:\Users\meito\MPLABXProjects\ATS-test-9-5.X\ATS-test-9-5.c
 1 /*************************************
 2    ATS-test-9-5
 3         PIC12F635
 4         2020/6/22
 5  ************************************/
 6 
 7 //#include <12f635.cgen.inc>
 8 #include <xc.h>
 9 
10 #define  _XTAL_FREQ  8000000
11 
12 #pragma config FOSC = INTOSCIO  // Oscillator Selection bits (INTOSCIO oscillator: I/O function on RA4/T1G/OSC2/CLKOUT pin, I/O function on RA5/T1CKI/OSC1/CLKIN)
13 #pragma config WDTE = OFF       // Watchdog Timer Enable bit (WDT disabled and can be enabled by SWDTEN bit of the WDTCON register)
14 #pragma config PWRTE = ON       // Power-up Timer Enable bit (PWRT enabled)
15 #pragma config MCLRE = OFF      // MCLR pin function select bit (MCLR pin function is alternate function, MCLR function is internally disabled)
16 #pragma config CP = OFF         // Code Protection bit (Program memory is not code protected)
17 #pragma config CPD = OFF        // Data Code Protection bit (Data memory is not code protected)
18 #pragma config BOREN = ON       // Brown-out Reset Selection bits (BOD enabled and SBOdEN bit disabled)
19 #pragma config IESO = OFF       // Internal-External Switchover bit (Internal External Switchover mode disabled)
20 #pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
21 #pragma config WURE = ON        // Wake-Up Reset Enable bit (Wake-up and Reset enabled)
22 
23 unsigned int flag;
24 unsigned int subflag;
25 
26 void main (){
27     OSCCON = 0x70;
28     CMCON0 = 0x07;
29     TRISIO = 0b00101000;
30     
31     flag=0;
32     subflag=0;
33     RA4=0;
34     
35     while(1){
36         if (RA5==1){
37             if(RA3==1){
38                 subflag=0;
39                 flag=0;
40                 RA0=1;
41                 RA1=0;
42                 RA2=0;
43                 RA4=1;
44             }else if(subflag==1){
45                 ;
46             }else if(flag==1){
47                 RA0=1;
48                 RA1=0;
49                 RA2=0;
50                 RA4=1;
51             }else{
52                 subflag=1;
53                 RA0=0;
54                 RA1=0;
55                 RA2=1;
56                 RA4=0;
57                 __delay_ms(1000);
58                 RA0=1;
59                 RA1=0;
60                 RA2=0;
61             }
62         }else if(RA3==1){
63             if(flag==1){
64                 flag=0;
65                 RA0=0;
66                 RA1=1;
67                 RA2=0;
68                 RA4=0;
69             }else{
70                 ;
71             }
72         }else if(subflag==1){
73             if(flag==1){
74                 ;
75             }else{
76                 subflag=0;
77                 flag=1;
78                 RA0=1;
79                 RA1=0;
80                 RA2=0;
81                 RA4=0;
82             }
83         }else if(flag==1){
84             ;
85         }else{
86             RA0=0;
87             RA1=0;
88             RA2=1;
89             RA4=0;
90         }
91     }
92 }
93